Error Recovery Mechanism using Dynamic Partial Reconfiguration
نویسندگان
چکیده
In this paper an error recovery mechanism for SRAM based FPGA systems is presented. Previous recovery methods employ processor cores as a reconfiguration controller consuming notable amount of device resources and introducing additional error detection and recovery latency. The described mechanism is controlled by a finite state machine architecture providing small hardware overhead and short recovery latency. The mechanism has been originally designed for mission critical applications with a required level of fault tolerance. However, it can also be used as a countermeasure to fault attack of faulttolerant secure devices.. Keywords— dynamic partial reconfiguration; FPGA; error mitigation; error recovery
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